It is well known that capacitors are critical components in today's integrated circuits. For example, capacitors play an important role in devices having analog circuits constructed on the integrated circuit chips, often being placed adjacent the device circuitry to carry out de-coupling functions. However, achieving the desired capacitance characteristics is often difficult due to several trends in the industry, namely increasing device density (e.g. VLSI designs) and increasing frequency of operating signals. First, since increased device densities has been achieved largely by the miniaturization of individual devices, it requires a similar miniaturization in capacitor structure, thereby placing a much greater importance on a high capacitance value per unit area. Second, higher operating frequencies have also increased the level of parasitic capacitance and cross-talk experienced between adjacent signal lines or metallization levels thereby increasing the demand upon many capacitors. However, fabrication of capacitance devices within or immediately adjacent the integrated circuit is often limited by VLSI design patterning rules. This is particularly true for capacitors intended for use in analog circuitry placed in immediate proximity to the metallization levels.
In light of the aforesaid requirements and limitations, present capacitor structures suffer from severe non-linearities (in capacitance value) caused by large voltage coefficient ratios (VCR), parasitic capacitances, resistances or combinations of the same. The existence of such non-linearities significantly limits the application and usefulness of the capacitor in analog circuits. However, solutions directed at improving the characteristics of such capacitors must comply with VLSI design patterning limitations, BEOL (back-end of the line) techniques, and spacial limitations. In addition, solutions complying with these requirements should not unduly increase the complexity of the device processing nor the cost of the resulting device. Thus, designs directed at addressing this problem have largely attempted to solve the problem using numerous masking and etching steps in the formation of the dielectric layers and multiple capacitor plates. Moreover, in order to comply with VLSI design patterning rules, commonly one of the capacitor plates will comprise doped polysilicon. In this regard such methods themselves suffer considerable drawbacks. Polysilicon materials offer significant resistances which become particularly problematic in devices having high frequency operating signals. Moreover, standard BEOL etches may often create structural irregularities that detract from the ability to repeatably and reliably fabricate a capacitor of a given capacitance value.
Therefore, there exists a need for a capacitive structure having high capacitance values per surface area that may be employed within integrated circuits, such as within the metallization levels of microelectronic devices. There further exists a need for a capacitive structure having a low VCR, in particular a VCR below 10 ppm/V. There further exists a need for a capacitive structure in which the capacitive value varies less than 1%. There further exists a need for a method of fabricating such capacitive structures that are compatible with VLSI design patterning rules, such as those using standard BEOL processing techniques. There further exists a need for such methods that allow reliable and repeatable fabrication of capacitive structures of a precise capacitance value.